High-speed data transceivers commonly include frequency divider circuits that convert a higher frequency to a lower frequency, i.e., divide a higher frequency down to a lower frequency. Such frequency divider circuits are commonly known as “divide-by-X” circuits, where X is a number. Most commonly, X is an integer. However, “fractional divider” circuits, in which X is not an integer, are also known. For example, divide-by-1.5 circuits are known.
High-speed data transceivers can include several frequency divider circuits that divide by several corresponding values of X. For example, transceiver can include a divide-by-2 circuit and a divide-by-4 circuit and other such divide-by-X circuits. A multiplexer can be included that selects which of the frequency divider circuits is to be utilized in response to operating conditions.
Fractional divider circuits are commonly based upon phase-locked loop (PLL) circuitry and can be somewhat complex, especially if a 50 percent duty cycle is generated. Circuit complexity can undesirably contribute to power dissipation and consume area on an integrated circuit chip.